1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor chip package which is acquired by connecting a semiconductor chip to another semiconductor chip or a substrate, and a manufacturing apparatus which is used in manufacturing the semiconductor chip package, and, more particularly, to a bonding apparatus which employs an ultrasonic bonding scheme and a manufacturing apparatus which is used to manufacture the semiconductor chip package.
2. Description of the Related Art
Recently, information communication systems in information communication networks which are expanding rapidly and globally demand enhanced capabilities and faster speed. In the packaging technology for semiconductor chips, high integration packaging techniques have been developed to meet the demand. As high integration packaging techniques which improve the performance of electronic devices make simultaneous bonding at multiple bonding points, it is important to achieve both the reliability and productivity.
Semiconductor chip packaging using an ultrasonic bonding technique is a promising technique to meet the requirements. Ultrasonic bonding is a technique which allows the to-be-bonded metal surface of a chip to contact the to-be-bonded metal surface of a mating part and applies ultrasonic vibration in a direction parallel to the contact surfaces to bond both. The ultrasonic bonding can bond metals in a shorter time in principle than other schemes.
Because of the advantage, studies have been made on the adaptation of this bonding scheme to bonding techniques, such as flip-chip bonding, face-down bonding and simultaneous bonding, as well as wire bonding, and practical usage of such adaptation for small chips is in progress. Adaptation to large chips, however, has not progressed yet so far. This is because as the number of pins to be bonded increases with an increase in the chip size, the input energy necessary for bonding increases, bringing about a serious problem of the wear-out of the mount tool which would not matter so much for small chips.
The wear-out of the mount tool will be discussed referring to the conceptual diagram of a semiconductor chip bonding apparatus using ultrasonic bonding shown in FIG. 1.
The mount tool has a capability of transferring an ultrasonic wave from ultrasonic vibration generating means to a to-be-bonded region via a semiconductor chip to be bonded while keeping applying holding force perpendicular to the contact surface to the semiconductor chip, and is a very important component for the ultrasonic bonding apparatus.
A semiconductor chip 12 is held by a mount tool 11 and another part 15 to be bonded to the semiconductor chip 12 is secured onto a stage 16 in a bonding process to such a degree that the part 15 does not cause friction with respect to the stage 16. With both bonding portions (13 and 14 in FIG. 1) in contact with each other, ultrasonic vibration is started. In general, at least one of the bonding portions 13 and 14 is a bump having such a structure as to protrude like a projection from the part, and the other part is the bump or a pad which is placed in a plate shape on a part.
When the area of a bonding region 17, a region where the bonding portions 13 and 14 are effectively coupled, increases as the bonding process progresses, sliding friction may occur at the interface between the mount tool 11 and the semiconductor chip 12. If ultrasonic vibration continues in this state, wear-out may occur on both the mount tool 11, which is kept applied with friction, and the semiconductor chip 12 at the contact surface thereof or a tool/chip contact surface 18. When such a situation is repeated, the wear-out of the mount tool 11 may go further in which case there is a possibility of causing improper bonding or causing a serious hindrance, such as damaging a part to be machined so that the replacement of the mount tool 11 is essential. At present, the replace period is short, which stands in the way of improving the productivity.
Many inventions have been presented so far to overcome the problem. A typical invention is disclosed in Japanese Patent Laid-Open No. 2002-164384 which is characterized by reducing the wear amount by specifying the material for the top surface of the mount tool.
However, such an invention is a symptomatic invention which cannot essentially prevent wearing and is not an essential solution to improvement of the productivity and reliability while it can make the replace period of the mount tool longer a little.